FIG. 1 shows a block diagram representation of an averaging circuit 100 as known in the prior art. The averaging circuit 100 inputs first and second input voltage signals V1 and V2 and generates an average voltage signal VA that is an average of the input voltage signals V1 and V2 as follows:VA=(V1+V2)/2.
FIG. 2 shows a circuit diagram of an example averaging circuit 100A formed with NMOSFETs (N-channel metal oxide semiconductor field effect transistors) according to the prior art. The example averaging circuit 100A includes a first NMOSFET M1, a second NMOSFET M2, a third NMOSFET M3, a fourth NMOSFET M4, a fifth NMOSFET MB1, and a sixth NMOSFET MB2.
The first and second NMOSFETs M1 and M2 are differentially coupled with the sources of the NMOSFETs M1 and M2 being coupled together to the fifth NMOSFET MB1 that provides a bias current Ib1. The third and fourth NMOSFETs M3 and M4 are differentially coupled with the sources of the NMOSFETs M3 and M4 being coupled together to the sixth NMOSFET MB2 that provides a bias current Ib2.
The first input voltage signal V1 is applied at a gate of the first NMOSFET M1, and the second input voltage signal V2 is applied at a gate of the third NMOSFET M3. The first and second NMOSFETs M1 and M2 are matched transistors, and the third and fourth NMOSFETs M3 and M4 are matched transistors. The fifth and sixth NMOSFETs MB1 and MB2 are matched transistors and have gates with a bias voltage VB applied thereon.
In that case, Ib1=Ib2. In addition, I1 which is a sum of the drain currents Id1 and Id3 through the first and third NMOSFETs M1 and M3, respectively, is equal to I2 which is a sum of the drain currents Id2 and Id4 through the second and fourth NMOSFETs M2 and M4, respectively. In this manner, if the transconductances gm1 and gm3 of the first and third NMOSFETs M1 and M3 are substantially equal, the average voltage signal VA is generated at the gates of the second and fourth NMOSFETs M2 and M4.
However, because only NMOSFETs are used in the averaging circuit 100A of FIG. 2, when V1 or V2 is lower than (Vth+ΔM1+ΔMB1), Ib1 may no longer be equal to Ib2. Vth is the threshold voltage of transistor M1, ΔM1 is a minimum drain to source saturation voltage of transistor M1, and ΔMB1 is a drain to source voltage of transistor MB1. Furthermore, if V1 or V2 is further lowered, then any of NMOSFETs M1, M2, M3, and M4 may be turned off. Thus, the averaging circuit 100A of FIG. 2 operates improperly for low values of V1 or V2.
FIG. 3 shows a circuit diagram of another example averaging circuit 100B having NMOSFETs and PMOSFETs (P-channel metal oxide semiconductor field effect transistors) for rail-to-rail voltage operation of the input voltage signals V1 and V2. The averaging circuit 100B of FIG. 3 includes first, second, third, fourth, fifth, and sixth NMOSFETs MN1, MN2, MN3, MN4, MBN1, and MBN2 configured similarly as the NMOSFETs of FIG. 2.
In addition, the averaging circuit 100B of FIG. 3 also includes first, second, third, fourth, fifth, and sixth PMOSFETs MP1, MP2, MP3, MP4, MBP1, and MBP2. The first and second PMOSFETs MP1 and MP2 are differentially coupled with the sources of the PMOSFETs MP1 and MP2 being coupled together to the fifth PMOSFET MBP1 that provides a bias current Ibp1 for the PMOSFETs MP1 and MP2. The third and fourth PMOSFETs MP3 and MP4 are differentially coupled with the sources of the PMOSFETs MP3 and MP4 being coupled together to the sixth PMOSFET MBP2 that provides a bias current Ibp2 for the PMOSFETs MP3 and MP4.
The first input voltage signal V1 is applied at gates of the first NMOSFET and PMOSFET MN1 and MP1, and the second input voltage signal V2 is applied at gates of the third NMOSFET and PMOSFET MN3 and MP3. The first and second NMOSFETs MN1 and MN2 are matched transistors, and the third and fourth NMOSFETs MN3 and MN4 are matched transistors. The fifth and sixth NMOSFETs MBN1 and MBN2 are matched transistors and have gates with a first bias voltage VBN applied thereon.
The first and second PMOSFETs MP1 and MP2 are matched transistors, and the third and fourth PMOSFETs MP3 and MP4 are matched transistors. The fifth and sixth PMOSFETs MBP1 and MBP2 are matched transistors and have gates with a second bias voltage VBP applied thereon.
In addition, I1 which is a sum of the drain currents through the first and third NMOSFETs MN1 and MN3 is equal to I2 which is a sum of the drain currents through the second and fourth NMOSFETs MN2 and MN4. Furthermore, I3 which is a sum of the drain currents through the first and third PMOSFETs MP1 and MP3 is equal to I4 which is a sum of the drain currents through the second and fourth PMOSFETs MP2 and MP4.
The transconductances gmn1 and gmn3 of the first and third NMOSFETs MN1 and MN3 are substantially equal, and the transconductances gmp1 and gmp3 of the first and third PMOSFETs MP1 and MP3 are substantially equal. In that case, the average voltage signal VA is generated at the gates of the second and fourth NMOSFETs MN2 and MN4 and the second and fourth PMOSFETs MP2 and MP4.
The NMOSFETs MN1, MN2, MN3, MN4, MBN1, and MBN2 operate for the higher levels of the input voltage signals V1 and V2. The PMOSFETs MP1, MP2, MP3, MP4, MBP1, and MBP2 operate for the lower levels of the input voltage signals V1 and V2. Thus, the averaging circuit 100B of FIG. 3 operates for the rail-to-rail voltage range of VDD to GND (ground) with VDD being applied at the sources of the bias PMOSFETs MBP1 and MBP2 and with GND being applied at the sources of the bias NMOSFETs MBN1 and MBN2.
However, an offset is generated in the average voltage signal VA for the averaging circuit 100B of FIG. 3 for some values of V1 and V2. For example, assume that V2<(Vthn+Δn3+Δnb2) with Vthn being the NMOSFET threshold voltage, Δn3 being a minimum drain to source saturation voltage of NMOSFET MN3, and Δnb2 being a drain to source voltage of NMOSFET MBN2. In addition, assume that V1<(Vthn+Δn1+Δnb1) with Vthn being the NMOSFET threshold voltage, Δn1 being a minimum drain to source saturation voltage of NMOSFET MN1, and Δnb1 being a drain to source voltage of NMOSFET MBN1.
In that first case, NMOSFETs MN1 and MBN1 operate in saturation, but NMOSFETs MN3 and MBN2 operate in the linear or cut-off region. Thus, a bias current Ibn2 through the bias NMOSFET MBN2 is decreasing. To maintain I1=I2, the average voltage signal VA is increased to be higher than (V1+V2)/2.
In another example, assume that V2<Vthn and that Vthn<V1<(Vthn+Δn1+Δnb1). In that second case, MN1 and MBN1 are not operating in saturation, but a small level of the bias current Ibn1 through the bias NMOSFET MBN1 exists. In addition, the NMOSFETs MN3 and MBN2 are in the cut-off region. To maintain I1=I2, the average voltage signal VA is increased to be higher than (V1+V2)/2.
In a further example, assume that V2<VDD−(Vthp+Δp3+Δpb2) with Vthp being the PMOSFET threshold voltage, Δp3 being a minimum source to drain saturation voltage of PMOSFET MP3, and Δpb2 being a source to drain voltage of PMOSFET MBP2. In addition, assume that V1>VDD−(Vthp+Δp1+Δpb1) with Vthp being the PMOSFET threshold voltage, Δp1 being a minimum source to drain saturation voltage of PMOSFET MP1, and Δpb1 being a source to drain voltage of PMOSFET MBP1.
In that third case, PMOSFETs MP3 and MBP2 operate in saturation, but PMOSFETs MP1 and MBP1 operate in the linear or cut-off region. Thus, a bias current Ibp1 through the bias PMOSFET MBP1 is decreasing. To maintain I1=I2, the average voltage signal VA is decreased to be lower than (V1+V2)/2.
In another example, assume that [VDD−(Vthp+Δp3+Δpb2)]<V2<(VDD−Vthp) and that V1>(VDD−Vthp). In that fourth case, MP3 and MBP2 are not operating in saturation, but a small level of the bias current Ibp2 through the bias PMOSFET MBP2 exists. In addition, the PMOSFETs MP1 and MBP1 are in the cut-off region. To maintain I1=I2, the average voltage signal VA is decreased to be lower than (V1+V2)/2.
FIG. 4 illustrates the positive offset Voff1 in the average voltage signal VA generated in FIG. 3 for the first and second example cases described above for lower values of an input voltage signal V1 or V2. FIG. 4 also illustrates the negative offset Voff2 in the average voltage signal VA generated in FIG. 3 for the third and fourth example cases described above for higher values of an input voltage signal V1 or V2.
Thus, a mechanism is desired for eliminating such offsets Voff1 and Voff2 to the average voltage signal VA in the rail-to-rail averaging circuit.